Now a day’s data storage is gainingmore importance in human life. All electronic and digital devices need memoryfor reducing the power consumption. The concept of “more data in less space” isuseful for increasing the system performance and overall system efficiency.

Generally we used semiconductor memory as “SRAM”. SRAM can be abbreviated”Static Random Access Memory”. Many VLSI chip can have SRAM memory because oftheir large storage capacity and fast accessing time. Where the word staticindicates that it does not need to be periodically refreshed but the DRAM needperiodically refreshed. DRAM can be abbreviated as “Dynamic Random AccessMemory” which is another type of memory. Both the memories can be classifiedfrom “Random Access Memory: (RAM).

 Inthis paper the power analysis of 6 transistor SRAM is compared with 7transistor   SRAM. As a result the power dissipationof 7 transistors is high when compared with 6 transistors. The powerdissipation of 6T SRAM is about 2.

991mW and the power dissipation of 7T SRAM isabout 3.183Mw. SRAM are mostly used for mobile applications, because of theirease of use and low leakage of power. In this paper the schematic of 6T SRAMand 7T SRAM are drawn using DSCH software and the layouts are drawn usingMICROWIND software.1. INTRODUCTION      Inrecent days, Static Random Access Memory has become the major role in digitalworld.

Because which occupies the largest part of SOC (system-on-chip). The majordevice need SRAM memory mainly for device dissipate small amount of power. Butthe dynamic power dissipation causes problems  in digital circuits because the dynamic powerdepends on supply voltage, switching frequency and output voltage swing.

Dynamic power dissipation can be minimized by reducing the supply voltage. Atthe same time low supply voltage leads to performance degradation and alsodecreases the threshold voltage which in turn increases the sub thresholdcurrent hence the static power dissipation increases. This paper discuss aboutthe power dissipation of 6 transistors and 7 transistors SRAM. It also includesthe functional view of 6T and 7T SRAM cells.   2. 6T STATIC RANDOM ACCESS MEMORY     A conventional 6T SRAMconsists 6 transistors which form two cross coupled inverters. This bit cellcan be read and write single bit data.

When a bit is stored in memory the 6TSRAM behave like a latch. The cross coupled inverter pattern which causes largearea consumption which is a drawback of 6T SRAM when compared to resistive load.Conventional SRAM with 6 transistors is shown in figure 1 and 6T SRAM havethree states they are read, write and hold states. 2.1. Hold StateWhenwrite operation (WL=0) the accessible transistor M1 and M2 disconnect the cellfrom bit lines. The leakage current can be drawn from vdd.2.

2. Read State     Theaccessible transistor M3 and M6 should be ON when pre-charging bit and bit barline to high.2.3 Write state      When the WL=0, the value to be written tothe bit and bit bar line.

Hence we write a data value is “0”, we take bit valueis “0” and bit bar value is “1”.and the data value is “1”, we take bit valueshould be “1” and the bit bar value is “0”.                                                                 3.7T STATIC RANDOM ACCESS MEMORY     As like 6T SRAM, the 7T SRAM circuit alsoconsists of two CMOS cross coupled to each other. In this circuit weadditionally connect NMOS transistor to write line.

And it also have two passNMOS transistor connected to the bit and bit bar line. The access transistor N3and N4 which are correspondingly connected to the write and read line toperform the write and read operation. Before write operation the 7T SRAM celldepends upon feedback connection. These feedback connection and disconnectioncan be performed by N5 transistor.3.1. Write Operation Thewrite operation can be start by turning off the N5 transistor to this cut offfeedback connection. When N3 is on and N4 is off the bit line bar carriescomplement of input data.

The N5 is turned on and WL is turned off forreconnect the feedback connection to store new data. The bit line bar isdischarged to “0” for storing “1” in the cell. And there is no need todischarge bit line for storing “0” in the cell.

3.2. ReadOperation      When performing the read operationboth read and word line are turned to on and also the transistor N5 is kept on. 4. RESULTS ANDDISCUSSION                                              Here we analysis and discuss about the 6T and 7T SRAM cell during readand write operation.

And the schematic view of SRAM cell is designed andimplemented by using DSCH and MICROWIND software.