The programmable interconnect points (PIP)
consists of one pass-gate , its usage is determined by the nature of FPGA
routing architectures. The buffered PIP is commonly used for degrading of past
transistors in series by reducing the associated signal. In Virtex-II pro
routing architecture there are unidirectional direct neighbour, double and hex
lines with all buffered PIP in single direction Whereas there are bidirectional
long lines having buffers in two directions. An interconnect model of a net is
shown by figure.
There are 5 different fundamentals present
in this parasitic model that is
Cell input/output pins
The wire length is measured by the distance
between 1 tile and the closest tile. When a wire goes to input cell after
coming from switch matrix having same parameters the case is assumed to be
worst for input cross bar. When there is comparison between the capacity of
crossbar or wire with the capacity of the cell ip/op pins comes out to be less.
For setting the values of this parasitic model Infineon 130nm CMOS six-layer is
used. An interconnect delay is reduced and is determined by the shrinking
factor of the MPGA in comparison o FPGA. Due to no delay in pass-gates in MPGA,
we can inserts buffers anytime according to the requirement.
Initially neglecting PIP and buffer and
considering only a wire by using 130nm technology parameters for metal and
analysis is done. Further a number is assumed to be calculated by the root
square of area in the analysis and is considered as a length of 173micrometer
for the Virtex-II pro. When the delay is measured in Virtex-II pro it is about
5ps whereas zelix MPGA it is 2ps as its wire length is 64% less. So in case of
long wire delay plays an important role.
SGA analysis is used to compare the result
of interconnect model. Using synopsis Nanosim circuit level simulations are
performed. the results are determined by the following cases