Interconnect model The programmable interconnect points (PIP)consists of one pass-gate , its usage is determined by the nature of FPGArouting architectures. The buffered PIP is commonly used for degrading of pasttransistors in series by reducing the associated signal. In Virtex-II prorouting architecture there are unidirectional direct neighbour, double and hexlines with all buffered PIP in single direction Whereas there are bidirectionallong lines having buffers in two directions.
An interconnect model of a net isshown by figure. There are 5 different fundamentals presentin this parasitic model that is · Wire· Input crossbar· Output crossbar· Cell input/output pins· Input/output padsThe wire length is measured by the distancebetween 1 tile and the closest tile. When a wire goes to input cell aftercoming from switch matrix having same parameters the case is assumed to beworst for input cross bar.
When there is comparison between the capacity ofcrossbar or wire with the capacity of the cell ip/op pins comes out to be less.For setting the values of this parasitic model Infineon 130nm CMOS six-layer isused. An interconnect delay is reduced and is determined by the shrinkingfactor of the MPGA in comparison o FPGA.
Due to no delay in pass-gates in MPGA,we can inserts buffers anytime according to the requirement.Initially neglecting PIP and buffer andconsidering only a wire by using 130nm technology parameters for metal andanalysis is done. Further a number is assumed to be calculated by the rootsquare of area in the analysis and is considered as a length of 173micrometerfor the Virtex-II pro. When the delay is measured in Virtex-II pro it is about5ps whereas zelix MPGA it is 2ps as its wire length is 64% less. So in case oflong wire delay plays an important role.
SGA analysis is used to compare the resultof interconnect model. Using synopsis Nanosim circuit level simulations areperformed. the results are determined by the following cases