Intel 8086

Intel 8086
.

Introduction:
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978, when it was released. The Intel 8088, released in 1979, is a slightly modified chip with an external 8-bit data bus,and is notable as the processor used in the original IBM PC design, including the widespread version called IBM PC XT.

We Will Write a Custom Essay Specifically
For You For Only $13.90/page!


order now

The 8086 gave rise to the x86 architecture, which eventually became Intel’s most successful line of processors.

In 1972, Intel launched the 8008, the first 8-bit microprocessor.It implemented an instruction set designed by Data point corporation with programmable CRT terminals in mind, which also proved to be fairly general-purpose. The device needed several additional ICs to produce a functional computer, in part due to it being packaged in a small 18-pin ;memory package;, which ruled out the use of a separate address bus (Intel was primarily a DRAM manufacturer at the time).

Two years later, Intel launched the 8080,employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It has an extended instruction set that is source-compatible (not binary compatible) with the 8008 and also includes some 16-bit instructions to make programming easier. The 8080 device, was eventually replaced by the depletion-load-based 8085 (1977), which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips.Other well known 8-bit microprocessors that emerged during these years are Motorola 6800 (1974), General Instrument PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80(1976), and Motorola 6809 (1978).

.

.Processor.Design:
.Pipelining.and.Five.stages.of.Architecture.is.where.the.various.parts.of.the.processor.are.split.up.into.separate.units.so.that.they.can.all.be.busy.at.the.same.time.

In.the.processor,.there.are.usually.several.different.steps.involved.in.executing.and.retiring.an.instruction..Such.steps.could.include:
Fetching instruction from memory/cache
Decoding the instruction
Load Registers
ALU stages
Store Register
.

.

.

Basic.Element.of.Processor.Design
Instruction.set:
The.8086.microprocessor.supports.8.types.of.instructions.

Data.Transfer.Instructions
Arithmetic.Instructions
Bit.Manipulation.Instructions
String.Instructions
Program.Execution.Transfer.Instructions.(Branch.;.Loop.Instructions)
Processor.Control.Instructions
Iteration.Control.Instructions
Interrupt.Instructions
1.Data.Transfer.Instructions
·.MOV.?.Used.to.copy.the.byte.or.word.from.the.provided.source.to.the.provided.destination.

·.PPUSH.?.Used.to.put.a.word.at.the.top.of.the.stack.

·.POP.?.Used.to.get.a.word.from.the.top.of.the.stack.to.the.provided.location.

·.PUSHA.?.Used.to.put.all.the.registers.into.the.stack.

·.POPA.?.Used.to.get.words.from.the.stack.to.all.registers.

·.XCHG.?.Used.to.exchange.the.data.from.two.locations.

·.XLAT.?.Used.to.translate.a.byte.in.AL.using.a.table.in.the.memory.

2.Arithmetic.Instructions
These.instructions.are.used.to.perform.arithmetic.operations.like.addition,.subtraction,
.division,.etc.

·.ADD.?.Used.to.add.the.provided.byte.to.byte/word.to.word.

·.ADC.?.Used.to.add.with.carry.

·.INC.?.Used.to.increment.the.provided.byte/word.by.1.

·.SUB.?.Used.to.subtract.the.byte.from.byte/word.from.word.

·.SBB.?.Used.to.perform.subtraction.with.borrow.

·.DEC.?.Used.to.decrement.the.provided.byte/word.by.1.

·.MUL.?.Used.to.multiply.unsigned.byte.by.byte/word.by.word.

·.DIV.?.Used.to.divide.the.unsigned.word.by.byte.or.unsigned.double.word.by.word.

·.IDIV.?.Used.to.divide.the.signed.word.by.byte.or.signed.double.word.by.word.

3.Bit.Manipulation.Instructions
·.NOT.?.Used.to.invert.each.bit.of.a.byte.or.word.

·.AND.?.Used.for.adding.each.bit.in.a.byte/word.with.the.corresponding.bit.in.another.byte·
.OR.?.Used.to.multiply.each.bit.in.a.byte/word.with.the.corresponding.bit.in.another.byte.

·.XOR.?.Used.to.perform.Exclusive-OR.operation.over.each.bit.in.a.byte/word.with.the.corresponding.bit.in.another.byte/word.

·.TEST.?.Used.to.add.operands.to.update.flags,.without.affecting.operands.

4.String.Instructions
·.REP.?.Used.to.repeat.the.given.instruction.till.CX.?.0.

·.REPE/REPZ.?.Used.to.repeat.the.given.instruction.until.CX.=.0.or.zero.flag.ZF.=.1.

·.REPNE/REPNZ.?.Used.to.repeat.the.given.instruction.until.CX.=.0.or.zero.flag.ZF.=.1.

·.MOVS/MOVSB/MOVSW.?.Used.to.move.the.byte/word.from.one.string.to.another.

·.COMS/COMPSB/COMPSW.?.Used.to.compare.two.string.bytes/words.

·.INS/INSB/INSW.?.Used.an.input.string/byte/word.from.the.I/O.port.to.the.provided.memory
·.SCAS/SCASB/SCASW.?.Used.to.scan.a.string.and.compare..string.word.with.a.word.in.AX.

·.LODS/LODSB/LODSW.?.Used.to.store.the.string.byte.into.AL.or.string.word.into.AX.

5.Program.Execution.Transfer.Instructions.(Branch.and.Loop.Instructions)
·.JA/JNBE.?.Used.to.jump.if.above/not.below/equal.instruction.satisfies.

·.JAE/JNB.?.Used.to.jump.if.above/not.below.instruction.satisfies.

·.JBE/JNA.?.Used.to.jump.if.below/equal/.not.above.instruction.satisfies.

·.JC.?.Used.to.jump.if.carry.flag.CF.=.1
·.JE/JZ.?.Used.to.jump.if.equal/zero.flag.ZF.=.1
·.JG/JNLE.?.Used.to.jump.if.greater/not.less.than/equal.instruction.satisfies.

·.JGE/JNL.?.Used.to.jump.if.greater.than/equal/not.less.than.instruction.satisfies.

·.JL/JNGE.?.Used.to.jump.if.less.than/not.greater.than/equal.instruction.satisfies.

·.JLE/JNG.?.Used.to.jump.if.less.than/equal/if.not.greater.than.instruction.satisfies.

·.JNC.?.Used.to.jump.if.no.carry.flag.(CF.=.0)
·.JNE/JNZ.?.Used.to.jump.if.not.equal/zero.flag.ZF.=.0
·.JNO.?.Used.to.jump.if.no.overflow.flag.OF.=.0
·.JNP/JPO.?.Used.to.jump.if.not.parity/parity.odd.PF.=.0
·.JNS.?.Used.to.jump.if.not.sign.SF.=.0
·.JO.?.Used.to.jump.if.overflow.flag.OF.=.1
·.JP/JPE.?.Used.to.jump.if.parity/parity.even.PF.=.1
6.Processor.Control.Instructions
·.STC.?.Used.to.set.carry.flag.CF.to.1
·.CLC.?.Used.to.clear/reset.carry.flag.CF.to.0
·.CMC.?.Used.to.put.complement.at.the.state.of.carry.flag.CF.

·.STD.?.Used.to.set.the.direction.flag.DF.to.1
·.CLD.?.Used.to.clear/reset.the.direction.flag.DF.to.0
·.STI.?.Used.to.set.the.interrupt.enable.flag.to.1,.i.e.,.enable.INTR.input.

·.CLI.?.Used.to.clear.the.interrupt.enable.flag.to.0,.i.e.,.disable.INTR.input.

7.Iteration.Control.Instructions
·.LOOP.?.Used.to.loop.a.group.of.instructions.until.the.condition.satisfies,.i.e.,.CX.=.0
·.LOOPE/LOOPZ.?.Used.to.loop.a.group.of.instructions.till.it.satisfies.ZF.=.1.;.CX.=.0
·.LOOPNE/LOOPNZ.?.Used.to.loop.a.group.of.instructions.till.it.satisfies.ZF.=.0.;.CX.=.0
·.JCXZ.?.Used.to.jump.to.the.provided.address.if.CX.=.0
8.Interrupt.Instructions
·.INT.?.Used.to.interrupt.the.program.during.execution.and.calling.service.specified.

·.INTO.?.Used.to.interrupt.the.program.during.execution.if.OF.=.1
·.IRET.?.Used.to.return.from.interrupt.service.to.the.main.program
Instruction.Encoding:
Encoding.of.instruction.must.include.opcode,.operands.;.addressing.information.Encoding:.represent.entire.instruction.as.a.binary.value.

decide.on.form.;.number.of.bytes
find.opcode.bits.from.table
decide.on.remaining.bits
individual.bit.values
look.up.mod.;.r/m.values.if.needed
look.up.register.encoding.if.needed
fill.opcode.byte(s)
add.immediate.operand.data.byte(s)
…words.à.little.endian
a..dest.precedes.source
.

Register.and.special.feature:.

General.Registers.or.General.Purpose.Registers.are.a.kind.of.registers.which.can.store.both.data.and.addresses..All.general.registers.of.the.8086.microprocessor.can.be.used.for.arithmetic.and.logic.operations.

The.8086.has.14.16.bits.registers..AX,.BX,.CX,.DX,.SI,.DI,.BP,.SP,.CS,.DS,.SS,.ES,.IP.and.the.flags.register..The.last.two.are.only.accessed.indirectly.

.Features:
.It.is.16.bit.processor..So.that.it.has.16.bit.ALU,.16.bit.registers.and.internal.data.bus.and.16.bit.external.data.bus..It.make.s.faster.processing..

.2..It.has.three.version.based.on.the.frequency.of.operation:
·.8086.-;.5MHz
·.8086-2.-;8MHz
·.8086-1.-;10.MHz
.3..8086.has.20.bit.address.lines.to.access.memory..Hence.it.can.access.

.2^20.=.1.MB.memory.location.

.

.4..8086.has.16-bit.address.lines.to.access.I/O.devices,.hence.it.can.access
.2^16.=.64K.I/O.location
.

.5..8086.uses.two.stage.of.pipelining..First.is.Fetch.Stage.and.the.second.is.Execute.Stage.

·.Fetch.stage.that.prefetch.upto.6.bytes.of.instructions.stores.them.in.the.queue.

·.Execute.stage.that.executes.these.instructions.

·.Pipelining.improves.the.performance.of.the.processor.so.that.operation.is.faster.

.

.6..Operates.in.two.modes:-8086.operates.in.two.modes:
a)Minimum.Mode:.A.system.with.only.one.microprocessor.

b)Maximum.Mode:-A.system.with.multiprocessor.

.

.7..8086.uses.memory.banks:-The.8086.uses.a.memory.banking.system..It.means.entire.data.is.not.stored.sequentially.in.a.single.memory.of.1.MB.but.memory.is.divided.into.two.banks.of.512KB.

.

.8..Interrupts:-8086.has.256.ve Actored.interrupts.

.

.9..Multiplication.And.Division:-8086.has.a.powerful.instruction.set..

So.that.it.supports.Multiply.and.Divide.operation.

Data.Flow.Diagram:.

.

Processor Design Analysis
CPI estimation:.

In.computer.architecture,.instructions.per.cycle(IPC).is.one.aspect.of.a.processor’s.performance
The.average.number.of.instruction.executed.for.each.clock.cycle..It.is.the.multiplicative.inverse.of.cycles.per.instruction.

Global.CPI=Clock.per.Instruction
Clock.Rate=Processor.Frequency
CPI.Time=Time.Required.How.Much.Global.CPI.Want
Number.of.Instruction=Per.Cycle
Example:
The.processor.8086,.which.frequency.7.MHz,.and.application.X.that.works.in.order.of.107.instruction.per.cycle..Calculate.Global.CPI.for.a.time.given 1.5×10-2.seconds.

Solution:
Clock.Rate=7.MHzCPI.Time=1.5×10-2No.of.Instruction=107Global.CPI=CPI.Time.×Clock.RateNo.of.InstructionGlobal.CPI=1.5×10-2×7×106107Global.CPI=1.05×10-2CPI for Two Applications:
Program.1:
For.the.multi-cycle.MIPS.Load.5.cycles.Store.4.cycles.R-type.4.cycles.Branch.3.cycles.Jump.3.cycles..If.a.program.has.50%.R-type.instructions.10%.load.instructions.20%.store.instructions.8%.branch.instructions.2%.jump.instructions.then.what.is.the.CPI?
Solution:
CPI=(4×50+5×10+4×20+3×8+3×2)/100=3.6Program.2:
For.the.multi-cycle.MIPS.Load.7.cycles.Store.9.cycles.R-type.3.cycles.Branch.6.cycles.Jump.5.cycles..If.a.program.has.20%.R-type.instructions.40%.load.instructions.50%.store.instructions.10%.branch.instructions.6%.jump.instructions.then.what.is.the.CPI?
Solution:
CPI=(9×50+7×40+3×20+6×10+5×6)/100=8.8So.Program.1.has.less.CPI.than.Program.2.CPI..It.is.clear.that.Program.1.CPI.3.6.is.the.ideal.CPI.for.Intel.8086.

Memory accesses/Instruction:
Memory access is aspect of mainframe structures that permits confident hardware associated structures to access major structure  HYPERLINK "https://en.wikipedia.org/wiki/Computer_storage" h memory, self-sufficient of the CPU.

Memory Access also utilized for evocation. Memory Access can divest costly evocation actions, for example bulky copy or  HYPERLINK "https://en.wikipedia.org/wiki/Vectored_I/O" h scatter-gather actions, from the CPU to a devoted memory access engine.

SPECINT is a CPU benchmark order for CPU integer development control. It is sustained by the Standard Performance Evaluation Corporation. SPECINT is the integer concert analysis module of the SPEC analysis collection. The initial SPEC analysis collection, CPU92, was stated in 1992. It was pursued by CPU95, CPU2000, and CPU2006. The most recent usual of SPECINT is CINT2006.

SPECINT analysis approved away on a broad variety of hardware, with effects usually published for the complete variety of structure-level executions utilize the newest CPUs. For SPECINT2006, CPUs contain Intel and AMD x86 & x86-64 mainframes, Sun SPARC, IBM POWER, and IA-64 CPU. If only CPU has many cores, only a particular core is used, hyper-threading is also usually halt.

Instruction Count:
Meant.for.a.particular.program.accumulated.to.sprint.on.a.particular.machine,has following.considerations:.

The.entire.accomplished.order.counts.up.of.the.program..

The.average.number.of.cycles.per.instruction..

Clock.cycle.of.machine.

CPI=Total program execution cyclesInstructions countCPU clock cycles=.Instruction.count×CPICPU execution time= CPU clock cycles×Clock cycle×Instruction count×CPI×Clock cycle T=I x CPI x CExample:
A Program is running on a specific machine (CPU) with the following parameters:
Total executed instruction count: 10,000,000 instructions.
Average CPI for the program: 2.5 cycles / instruction.
CPU clock rate: 200 MHz. (clock cycle = C = 5×10-9 seconds).
What is the execution time for this program?
Solution:
CPU time = Instruction count×CPI×Clock cycle = 10,000,000 x 2.5 x 1 clock rate = 10,000,000×2.5×5.0×10-9=0.125 seconds.

x

Hi!
I'm Belinda!

Would you like to get a custom essay? How about receiving a customized one?

Check it out